1. Field of the Invention
The present disclosure generally relates to semiconductor devices. More specifically, the present disclosure relates to workfunction tuning in CMOS devices.
2. Description of Related Art
Integrated circuits (ICs) are combinations of transistors and other components fabricated on wafers. Commonly, these wafers are semiconductor materials, and, in particular, silicon. Recently, transistors sizes have reduced in size to 45 nm and are continuing to shrink to 32 nm. The semiconductor industry remains focused on further reducing transistor size, however new challenges arrive with each size reduction.
Contacts to transistors in the ICs typically include materials with high conductance that allow signals to pass unimpeded from one destination to another. However, the transistors themselves are semiconductor devices, which may have a lower conductivity. Conventionally, metal-oxide-semiconductor field effect transistors (MOSFETs) are used in ICs. A MOSFET is often built on a p-doped or n-doped semiconductor bulk region and include regions of doped material referred to as a source or drain region. The bulk region between the source and drain is commonly referred to as a channel. Above the channel a gate stack is used to control current in the channel. For example, application of a suitable voltage to the gate with respect to the source inverts the region near the gate in the channel to provide carries of similar polarity to the source and drain regions allowing a flow of current from the source to drain. That is, the gate-source voltage controls, in part, the current flow through the channel referred to a drive current.
As transistor sizes shrink, the contact area between the source and drain regions and a metal contact for communicating with the transistor decreases proportionally. Contact resistance of the source and drain regions increases proportionally to a decrease in the contact area. Thus, smaller contact areas has led to higher contact resistances. Conventionally, the contact resistance is parasitic and degrades performance of the MOSFET. A portion of the contact resistance results from a Schottky barrier between the metal contact and the source and drain regions.
As described above, semiconductor materials often have low conductivity compared to other conducting materials. One alternative replaces the doped silicon in the source and drain regions with a conducting material such as metal, silicide, or nitride. A Schottky barrier forms at the boundary of the conducting material and the channel. The Schottky barrier has a built in barrier potential that acts as a rectifying junction similar to the diffused junction rectifier in MOSFETs with semiconductor source and drain regions as described earlier.
Replacing the semiconductor source and drain regions of low conductivity with a metal or silicide source and drain regions with higher conductivity can reduce the parasitic extension resistance. Yet further reducing parasitic resistance may be accomplished by lowering the Schottky barrier height of the MOSFET to reduce metal-semiconductor contact resistance. In both the MOSFET and SB-MOSFET, a Schottky barrier between a metal and a semiconductor reduces device performance by increasing contact resistance.
Current solutions for lowering the Schottky barrier include using dual metals, dual silicides, or interface engineering approaches. However, these approaches add significant complexity to the semiconductor manufacturing process, which increase cost and time of manufacturing.